The present invention relates generally to semiconductor technology and more specifically to annealing conductors in semiconductor processing.
In the manufacture of integrated circuits, after the individual devices such as the transistors have been fabricated in and on the semiconductor substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called xe2x80x9cmetalizationxe2x80x9d and is performed using a number of different photolithographic, deposition, and removal techniques.
Briefly, individual semiconductor devices are formed in and on a semiconductor substrate and a device dielectric layer is deposited. Various techniques are used to form gate and source/drain contacts, which extend up to the surface of the device dielectric layer. In a process called the xe2x80x9cdamascenexe2x80x9d technique, dielectric layers are deposited over the device dielectric layers and openings are formed in the dielectric layers. Conductor materials are deposited on the dielectric layers and in the openings. A process is used to planarize the conductor materials with the surface of the dielectric layers so as to cause the conductor materials to be xe2x80x9cinlaidxe2x80x9d in the dielectric layers.
More specifically for a single layer of interconnections, a xe2x80x9csingle damascenexe2x80x9d technique is used in which the first channel formation of the single damascene process starts with the deposition of a thin first channel stop layer over the device dielectric layer. The first channel stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the device contacts. The photoresist is then stripped. A first channel dielectric layer is formed on the first channel stop layer. Where the first channel dielectric layer is of an oxide material, such as silicon oxide (SiO2), the first channel stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched.
The first channel dielectric layer is then subject to further photolithographic process and etching steps to form first channel openings in the pattern of the first channels. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the first channel dielectric layer and lines the first channel openings to ensure good adhesion of subsequently deposited material to the first channel dielectric layer. Adhesion layers for copper (Cu) conductor materials are composed of compounds such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN).
These nitride compounds have good adhesion to the dielectric materials and provide fair barrier resistance to the diffusion of copper from the copper conductor materials to the dielectric material. High barrier resistance is necessary with conductor materials such as copper to prevent diffusion of subsequently deposited copper into the dielectric layer, which can cause short circuits in the integrated circuit. However, these nitride compounds also have relatively poor adhesion to copper and relatively high electrical resistance.
Because of the drawbacks, pure refractory metals such as tantalum (Ta), titanium (Ti), or tungsten (W) are deposited on the adhesion layer to line the adhesion layer in the first channel openings. The refractory metals are good barrier materials, have lower electrical resistance than their nitrides, and have good adhesion to copper.
In some cases, the barrier material has sufficient adhesion to the dielectric material that the adhesion layer is not required, and in other cases, the adhesion and barrier material become integral. The adhesion and barrier layers are often collectively referred to as a xe2x80x9cbarrierxe2x80x9d layer herein.
For conductor materials such as copper, which are deposited by electroplating, a seed layer is deposited on the barrier layer and lines the barrier layer in the first channel openings to act as an electrode for the electroplating process. Processes such as electroless, physical vapor, and chemical vapor deposition are used to deposit the seed layer.
A first conductor material is deposited on the seed layer and fills the first channel opening. The first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
A chemical-mechanical polishing (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first channel dielectric layer to form the first channels. When a layer is placed over the first channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and a xe2x80x9csinglexe2x80x9d damascene process is completed. When the layer is processed further for placement of additional channels over it, the layer is a via stop layer.
For more complex integrated circuits, a xe2x80x9cdual damascenexe2x80x9d technique is used in which channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes and interconnected by vertical connections, or xe2x80x9cviasxe2x80x9d.
More specifically, the dual damascene process starts with the deposition of a thin etch stop layer, or the via stop layer, over the first channels and the first channel dielectric layer. A via dielectric layer is deposited on the via stop layer. Again, where the via dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched.
Second channel stop and second channel dielectric layers are formed on the via dielectric layer. Again, where the second channel dielectric layer is of an oxide material, such as silicon oxide, the second channel stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The second channel and via stop layers and second channel and via dielectric layers are then subject to further photolithographic process, etching, and photoresist removal steps to form via and second channel openings in the pattern of the second channels and the vias.
An optional thin adhesion layer is deposited on the second channel dielectric layer and lines the second channel and the via openings.
A barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second channel openings and the vias.
Again, for conductor materials such as copper and copper alloys, a seed layer is deposited by electroless deposition on the barrier layer and lines the barrier layer in the second channel openings and the vias.
A second conductor material is deposited on the seed layer and fills the second channel openings and the vias.
A CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second channel dielectric layer to form the second channels. When a layer is placed over the second channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and the dual damascene process is completed.
The capping layer may be an etch stop layer and may be processed further for placement of additional levels of channels and vias over it. Individual and multiple levels of single and dual damascene structures can be formed for single and multiple levels of channels and vias, which are collectively referred to as xe2x80x9cinterconnectsxe2x80x9d.
The use of the single and dual damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum (Al) to other metalization materials, such as copper, which are very difficult to etch.
A major problem occurs during the annealing process of conductor layers, which have been deposited by electroplating. The annealing is desirable to cause grain growth, which results in desirable reduced resistivity and stress levels. The problem is that the annealing causes the coalescence of microscopic voids in the conductor layer into macroscopic voids which reduce the current carrying capability of the finished conductor core and potentially lead to early failures of the integrated circuit.
Solutions to this problem have been long sought but have long eluded those skilled in the art.
The present invention further provides a method for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to a two step timed anneal. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel.